Microelectronic devices are generally fabricated on semiconductor substrates as integrated circuits. A complementary metal-oxide-semiconductor (CMOS) field effect transistor is one of the core elements of the integrated circuits. Dimensions and operating voltages of CMOS transistors are continuously reduced, or scaled down, to obtain ever-higher performance and packaging density of the integrated circuits.
One of the problems due to the scaling down of CMOS transistors, is that the power consumption keeps increasing. This is partly because leakage currents are increasing (e.g. due to short channel effects) and because it becomes difficult to decrease the supply voltage. The latter is mainly due to the fact that the subthreshold slope is limited to minimally about 60 mV/decade, such that switching the transistor from ON to OFF needs a certain voltage variation and therefore a minimum supply voltage.
Tunnel field-effect transistors (TFETs) are typically advertised as successors of metal-oxide semiconductor field-effect transistors (MOSFETs), because of their absence of short-channel effects and because of their resulting low off-currents. Another advantage of TFETs is that the subthreshold slope can be less than 60 mV/dec, the physical limit of conventional MOSFETs, such that potentially lower supply voltages can be used. However, TFETs typically suffer from low on-currents, a drawback related to the large resistance of the tunnel barrier.
Silicon-based TFETs are the most attractive because they allow for a full re-use of the existing expertise in fabricating high-quality silicon-compatible gate dielectrics. However, the small band-to-band tunneling efficiency in large-bandgap silicon results in low on-currents of the all-silicon TFETs. To improve the on-currents while maintaining a silicon-channel, the incorporation of heterostructures has been proposed.
In EP1900681, a method of fabricating an improved TFET using nanowires is disclosed. The method comprises providing a source contact on a substrate, and growing on the source contact a nanowire structure having an integrated source region, a channel region, a heterosection, and a drain region. The source region, channel region and drain region are made from a first semiconductor material and the heterosection is made from a second material with a lattice constant which is different from the lattice constant of the first semiconductor material. The method further comprises selectively doping the source region, the channel region, the heterosection and the drain region to a desired doping level and dopant type, depositing on sidewalls of the nanowire structure a gate dielectric and a gate electrode, and forming a drain contact on top of the drain region of the nanowire.
Different TFET integration approaches exist. They can be classified on the one hand in top-down approaches, and on the other hand in bottom-up approaches. For the known top-down approaches, the bottom junction, the intrinsic doped Si and the top diode (in situ doped Si or heterostructures) are epitaxially grown before the nanowire patterning. Complementary devices need to have an epitaxial growth in two steps: one with P-top and one with N-top. An issue with known catalyst based bottom-up approaches is metal contamination. Therefore the nanowires can be selectively grown in an oxide template (growth in holes). This means selective growth of the intrinsic Si channel in situ, followed by the growth of the heterojunction which makes the integration scheme complex for complementary devices.